Quantum-dot Cellular Automata Research Articles

A review on regular clocking scheme in quantum dot cellular automata

Quantum-dot cellular automata (QCA) is a novel and emerging nanotechnology that explores the potential of using quantum dots as information carriers in computing devices. The information transfer, as well as timing synchronization of the QCA circuit, is controlled by clocks. Despite this, most of the work done in QCA does not consider the proper layout of the underlying clocking circuit required. Hence, it ends up with QCA circuits with irregular clock zones, which is not suitable for fabrication. However, for efficient design and to provide proper routing options within the clock zones, a regular, scalable clocking scheme is needed. Without a well-defined and regular clocking zone, the QCA circuit designs are incomplete and not a standard fabrication candidate. In this regard, several regular clocking schemes in QCA are discussed in the literature. In this survey, a systematic review of those clocking schemes will be investigated. A detailed comparison of these schemes is also discussed based on design architecture and fabrication point of view.

An Efficient Design of 2-BIT Arithmetic Logical Unit in Quantum Dot Cellular Automata

For the past two decades, CMOS technology has reigned supreme in the world of Very Large Scale Integration (VLSI). But Quantum Dot Cellular Automata (QCA) is stepping into the spotlight, offering a fresh solution to the growing challenges of CMOS. This paper delves into the potential of QCA circuits by presenting a 2-bit Arithmetic Logic Unit (ALU) crafted with this groundbreaking technology, while also benchmarking it against conventional CMOS designs. The proposed QCA-based ALU delivers a trifecta of benefits: streamlined circuit design, exceptional space efficiency, and reduced quantum cost—all while keeping performance sharp in terms of latency and area usage. This 2-bit ALU encompasses a suite of operations: addition, subtraction, multiplication, division, bitwise AND, OR, XOR, and XNOR. QCA technology addresses some of CMOS's major pain points, like slow switching speeds, and doesn't require additional power sources, making it both efficient and environmentally friendly. This is not just an incremental improvement; it's a bold leap into the future of circuit design

QCA-based Fault-Tolerant XOR Gate for Reliable Computing with High Thermal Stability

Abstract The XOR gate is an essential element in the design of digital circuits due to its versatility and usefulness. The design of XOR gate in this paper is based on Quantum-dot Cellular Automata (QCA) 2D planner technology with no line-to-line intersections. The output amplitude is improved by redundant cell-based design, which also helped reliability and fault tolerance outperform. The proposed XOR gate achieves fault tolerance to single-cell addition and missing-cell defects from 68.48% to 95.33%. In addition, the proposed XOR gate is also fault-tolerant against multiple-cell missing defects, as verified from the simulations. Furthermore, high thermal stability makes the circuit reliable for QCA-based digital design applications. The digital design applications such as 4-bit B2G code converter and a 4-bit parity checker are designed from this XOR gate, utilizing 438 and 414 cells, respectively. This demonstrates its effectiveness in designing fault resilient and reliable circuit designs for various applications.

An Efficient Design of a Three-Layer Magnitude Comparator for Nano-Scale IoT Applications Based on QCA Technology

The difficulty of further downscaling CMOS technology arises from the restriction of feature size reduction. Quantum-dot cellular automata (QCA) emerges as a paradigm-shifting successor to CMOS, heralding a new era of effective digital design at the nanoscale. It stands as an enticing frontier in nanoscale computing, with limited exploration into the realms of smaller QCA cells, elevated processing speeds, and more compact area requirements across diverse circuits. Within the intricate landscape of decoding circuits and process controllers, the binary comparator assumes a role of paramount significance. On the other hand, the quickly developing Internet of Things (IoT) market aims to produce high-speed, low-power gadgets. A comparator is a crucial component in the analog-to-digital conversion process used by IoT devices. In order to meet the power and latency requirements of IoT devices, a high-speed, low-power comparator is greatly required. Consequently, the strategic design of comparators within the QCA framework has ascended to a position of heightened importance in cutting-edge research. This study undertakes the formidable task of conceiving QCA-centric designs for MV32, the majority gate, and the inverter gate, thereby contributing to the development of a sophisticated multi-layered comparator architecture for IoT devices. In the realization of a three-layer comparator implemented in QCA, we attain an impressive feat—a minimal clock zone demanding only a singular clock pulse coupled with exceptional compaction (measuring at a mere 0.03 μm2). Experimental revelations corroborate the substantial advancement of the proposed design over traditional methodologies, particularly in terms of circuit area, cell count, and clock efficiency.

Design and Evaluation of a New Nanoscale and Cost-Efficient Coplanar Digital Parity Generator Based on Quantum Dots

A parity generator as a combinational logic circuit in digital circuits can generate the parity bit in the transmitter. It is very applicable in digital networking and communications. Also, rather than diodes and transistors, quantum dots will be used in the next-generation circuits. Quantum-dot Cellular Automata (QCA) offers a new platform where binary data is represented by polarized cells that are defined by the electron configurations. Therefore, a coplanar 4-bit parity generator is suggested in this work. This new arrangement eliminates complicated crossovers and provides complete access to all input and output pins. An XOR gate is used to implement the suggested architecture. Simulation waveforms and performance data confirm the proposed circuits’ functioning and advantages. The suggested four-bit parity generator uses less overhead than its equivalents. We simulated and tested the suggested circuit with the assistance of the QCADesigner 2.0.3 simulator. The QCADesigner software findings demonstrate that the suggested design is simpler and less expensive than earlier designs. Compared to the present best design, the suggested four-bit parity generator reduces cell number and latency by 55.29% and 40%, respectively.

A fault-tolerant QCA-based convolution encoder for robust data transmission

Metal oxide semiconductor (MOS) technology has reached its maximum profitable limits due to increase in leakage current, static power dissipation, limited switching frequency. One of the better solutions to overcome these problems is the quantum-dot cellular automata (QCA) technology, it boasts the absence of physical transportation charges, relying solely on Coulombic force for interaction between the cells also it is a transistor less technology does not require any external voltage bias. In the current integrated circuits, the data being transferred more than ever, the error correction and coding techniques find significance in reliable data communication. Recognizing the increasing importance of error correction in data communication, particularly with the widespread data transfer, this research specifically focuses on the implementation of an enhanced convolutional encoder using QCA for error correction in data transmission. Comparative study with the state-of-art is also carried out to examine performance of proposed design. As a result of our study, we were able to reduce the cell count by 33.34% and power dissipation is reduced by 77% with the proposed 1/2 rate encoder and the proposed 1/3 rate encoder has 15.9% less cell count and power dissipation is reduced by 72% as compared to existing design.

Implementations of efficient non-blocking crossbar network with novel multiplexer design in quantum-dot cellular automata

As an emerging nanotechnology, Quantum-dot Cellular Automata (QCA) has attracted extensive attentions due to its characteristics of high density, high speed, and low energy consumption. Modern high-performance System-on-Chips (SoCs) with multiple processors require interconnection networks to connect each core for improving data throughput and reducing latency, while the crossbar network is broadly used as a non-blocking interconnection architecture with high efficiency. In this paper, a method to design an efficient QCA-based N × N crossbar network utilizing optimally designed N:1 multiplexers (MUXs) is proposed, followed by a multi-layer and a single-layer implementation of its 8 × 8 design. A simplified matrix model is then introduced to provide a concise and intuitive switch control strategy, and expressions for cell count, area, latency, QCA cost, and QCA complexity of the proposed crossbar networks are derived according to the size N. Experimental results manifest that the proposed 8 × 8 crossbar networks have significant advantages on most performance parameters compared with other existing QCA-based networks.

Optimizing fault tolerance of RAM cell through MUX based modeling and design using symmetries of QCA cells

Extensive research is now being conducted on the design and construction of logic circuits utilizing quantum-dot cellular automata (QCA) technology. This area of study is of great interest due to the inherent advantages it offers, such as its compact size, high speed, low power dissipation, and enhanced switching frequency in the nanoscale domain. This work presents a design of a highly efficient RAM cell in QCA, utilizing a combination of a 3-input and 5-input Majority Voter (MV) gate, together with a 2 × 1 Multiplexer (MUX). The proposed design is also investigated for various faults such as single cell deletion, single cell addition and single cell displacement or misalignment defects. The circuit under consideration has a high degree of fault tolerance. The functionality of the suggested design is showcased and verified through the utilization of the QCADesigner tool. Based on the observed performance correlation, it is evident that the proposed design demonstrates effectiveness in terms of cell count, area, and latency. Furthermore, it achieves a notable improvement of up to 76.72% compared to the present configuration in terms of quantum cost. The analysis of energy dissipation, conducted using the QCAPro tool, is also shown for various scenarios. It is seen that this design exhibits the lowest energy dispersion, hence enabling the development of ultra-low power designs for diverse microprocessors and microcontrollers.

Advancing nanoscale computing: Efficient reversible ALU in quantum-dot cellular automata

This paper presents a significant contribution to the field of nanoscale computing by proposing an innovative reversible Arithmetic and Logic Unit (ALU) implemented in Quantum-Dot Cellular Automata (QCA). Reversible logic and QCA technology offer promising alternatives to conventional CMOS technology, addressing the challenges of operating at nanoscale dimensions. The primary objective is to develop a highly efficient ALU capable of performing 26 distinct arithmetic and logical operations. The ALU design is based on a novel reversible full adder-subtractor optimized for minimal quantum cost, which is crucial for energy-efficient quantum computation. The evaluation encompasses various criteria related to reversibility, such as gate count, number of constant inputs, number of garbage outputs, and quantum cost. QCA-specific criteria, including cell count, occupied area, and clock cycles, are also considered. The outcomes of this research contribute to the advancement of cell-efficient nanoscale computing, with implications for quantum computation, emerging technologies, and future integrated circuit design.

Design and Analysis of a New Fault-Tolerant QCA-based Nano-Scale Circuit for Morphological Operations in Image Processing

Quantum-dot cellular automata (QCA) is based on traditional cellular automata models in which each cell has one of the finite distinct states at any given time. Cellular automata refer to the use of Coulombic contact rather than wires to connect cells. The discrete character of cellular automata and quantum mechanics have been exploited to develop nano-scale devices that can conduct computations with high switching frequency and low power dissipation. QCA has been utilized in many categories for fault-tolerant and reversible logic computing. On the other hand, the morphology algorithm is an area of image processing that provides a unified methodology and strong tools for image/video processing applications. This work proposes a unique fault-tolerant approach based on QCA to execute the morphological operations in image processing. Two fault-tolerant 5-input majority gates are employed in the implemented QCA architecture, and a control line is used to accomplish dilation and erosion. To assess the capabilities of the proposed fault-tolerant circuit for morphological procedures, its performance is analyzed and confirmed. The proposed design is compared to earlier results, which significantly improve fault-tolerant ability.

Novel level and edge-triggered universal shift registers with low latency in QCA technology

Shift registers are one of the main blocks in processors. In this paper, two new universal shift registers are designed based on Quantum-Dot Cellular Automata (QCA) nanotechnology. Both of the proposed level triggered and edge triggered universal shift register in QCA technology shows good performance in regards of the number of cells, occupied area, delay, and power. These designs also have reset abilities. Simulations show that the proposed 4-bit level triggered universal shift register with reset ability has 1057 QCA cells, 1.27 μm2 occupied area, and delay of about three cycles of QCA clock. In addition, the proposed rising edge triggered 4-bit universal shift register with reset ability has 1085 QCA cells, 1.27 μm2 occupied area, and delay of about three cycles of QCA clocks.

A new nano-design of configurable logic module based on coplanar reversible adder and modified Fredkin gates using quantum technology

Quantum Dot Cellular Automata (QCA) and reversible logic have emerged as promising alternatives to conventional CMOS technology, offering several advantages, such as ultra-dense structures and ultra-low-power consumption. Among the crucial components of processors, the Arithmetic Logic Unit (ALU) has witnessed significant advancements in reversible computing, leading to energy-efficient and high-speed computing systems, particularly beneficial for Digital Signal Processing (DSP) applications. Conventional ALUs, reliant on irreversible logic, encounter energy inefficiencies due to information loss during computations, resulting in increased power consumption. Moreover, they may face limitations in processing speed, impacting real-time processing capabilities, especially for complex DSP tasks involving intensive arithmetic and logic operations. In response to these challenges, a research paper presents a pioneering approach, proposing a novel reversible ALU design using QCA nanotechnology. The proposed design ingeniously incorporates Modified Fredkin (MF) gates, and a coplanar reversible full adder based on the HNG gate, skillfully leveraging the unique features of QCA nanotechnology to optimize the ALU's energy-efficient and high-speed performance for DSP applications. This revolutionary QCA reversible ALU comprises 330 QCA cells arranged in a compact 0.41 μm2 area, skillfully realized through the coplanar clock-zone-based crossover approach. Its core computational elements, the three MF gates, and the innovative coplanar reversible full adder empower the ALU to execute a remarkable array of 20 distinct arithmetic and logic operations, showcasing its versatility in handling diverse DSP tasks. The proposed structure undergoes extensive simulations utilizing QCADesigner version 2.0.3 to confirm its performance. The evaluation results manifest substantial improvements compared to previous designs, boasting a 30% reduction in area occupancy, a 20% decrement in cell count, a 10% reduction in latency, and a 10% decrease in quantum cost compared to the best-known previous structure. These compelling outcomes solidify the potential of the proposed reversible ALU as a transformative advancement in energy-efficient and high-speed computing for DSP applications.

Ultra-optimized demultiplexer unit design in quantum-dot cellular automata nanotechnology

Integrated circuit designers face challenges in using complementary metal oxide semiconductor (CMOS) technology as it has a large leakage current and scalability challenge in ultra-nanoscale regime. Quantum-dot Cellular Automata (QCA) is a nanotechnology that can replace CMOS for designing ultra-deep submicron circuits and overcoming CMOS limitations. In this research paper, a novel area-efficient 1:2 demultiplexer is proposed using QCA technology. A demultiplexer is an important combinational circuit used in communication systems and computer memories. It receives serial input data and routes data in parallel to multiple outputs. QCA Designer and QCA Pro-tools are used for layout, simulation, and analysis of power dissipation. 11 QCA cells are utilized in the construction of the proposed 1:2 demultiplexer. The cell area and layout cost of the proposed demultiplexer have improved to 42.11 % and 55.56 % of the current best design, respectively. An essential factor to consider when developing integrated circuits is power dissipation. The proposed design dissipates less power. The energy dissipation of the proposed design has improved to 57.67 % at the kink energy level of 1.5 of the current best design.

An Ultra-Energy-Efficient Reversible Quantum-Dot Cellular Automata 8:1 Multiplexer Circuit

Energy efficiency considerations in terms of reduced power dissipation are a significant issue in the design of digital circuits for very large-scale integration (VLSI) systems. Quantum-dot cellular automata (QCA) is an emerging ultralow power dissipation approach, distinct from traditional, complementary metal-oxide semiconductor (CMOS) technology, for building digital computing circuits. Developing fully reversible QCA circuits has the potential to significantly reduce energy dissipation. Multiplexers are fundamental elements in the construction of useful digital circuits. In this paper, a novel, multilayer, fully reversible QCA 8:1 multiplexer circuit with ultralow energy dissipation is introduced. The power dissipation of the proposed multiplexer is simulated using the QCADesigner-E version 2.2 tool, describing the microscopic physical mechanisms underlying the QCA operation. The results show that the proposed reversible QCA 8:1 multiplexer consumes 89% less energy than the most energy-efficient 8:1 multiplexer circuit previously presented in the literature.

Fault-tolerant universal reversible gate design in QCA nanotechnology

Quantum-dot cellular automata (QCA) nanotechnology is the best suited technology for the nanocomputing applications. The limitations of the conventional transistors in nanoscale region can be removed by QCA nanotechnology. Hence, this paper proposes a novel design and implementation of a 3 × 3 universal and reversible gate in QCA nanotechnology. The proposed gate requires only 39 cells and has a total area of 0.029 µm2 with a latency of 0.25. The proposed gate is evaluated for the various possible defects and the performance parameters. The proposed gate is also compared with the existing gates and the proposed gate is established as the most efficient and productive.

Novel energy efficient RND inverter using quantum dot cellular automata in nanotechnology

Quantum-Dot Cellular Automata (QCA) is a promising technology for designing high-performance and efficient logic circuits, surpassing traditional Complementary Metal Oxide Semiconductor approaches. In today’s digital era, the demand for digital circuits with high speed, device density, and energy efficiency is paramount. This paper focuses on the innovative Rotated Normal Cells with Displacement (RND) inverter model, employing normal and rotated cells with a 10 nm displacement through a cell interactive method. Digital circuits designed using the RND inverter exhibit superior performance compared to existing designs. The proposed RND inverter gate utilizes only four QCA cells, occupying a total area of 4525.55 nm2. With a total energy dissipation of 0.508 meV and an average energy dissipation per cycle of 0.0462 meV, it achieves a polarization of 9.77. The novel RND inverter demonstrates a 44% improvement in cell area and a 63% reduction in total area compared to current designs, offering enhanced energy efficiency with 0.26 improved polarization. The RND inverter and the digital circuits facilitate finding applications in efficiently constructing various components within Quantum Computers. Beyond quantum computing, the RND inverter proves applicable in designing Nano-sized electronic gadgets and temperature-controlled circuits, showcasing its versatility across diverse technological applications.

Notice of Violation of IEEE Publication Principles: Design of Cost Efficient Modular Digital QCA Circuits using Optimized XOR Gate

Notice of Violation of IEEE Publication Principles “Design of Cost Efficient Modular Digital QCA Circuits using Optimized XOR Gate” by Suhaib Ahmed and Syed Farah Naz in IEEE Transactions on Circuits and Systems II: Express Briefs After careful and considered review of the content and authorship of this paper by a duly constituted expert committee, this paper has been found to be in violation of IEEE’s Publication Principles. This paper contains significant portions of original text from the paper cited below. The original text was copied without attribution (including appropriate references to the original author(s) and/or paper title) and without permission. “Design and Analysis of a Novel Low-Power Exclusive-OR Gate Based on Quantum-Dot Cellular Automata” By Haotian Chen, Hongjun Lv, Zhang Zhang, Xin Cheng and Guangjun Xie in Journal of Circuits, Systems, and Computers, Vol. 28, No. 8, 2017 The advantages such as high operating frequency (in the range of few THz), low power dissipation, small size and high density in the nano regime has led to the application of Quantum dot Cellular Automata (QCA) in designing various digital circuits. In this brief, an ultra-efficient two input XOR gate design in QCA is proposed. It is a single layer design consisting of only 9 cells with no crossover and operating on cell to cell interaction. The functionality of the proposed gate has been verified at both physical and simulation level. In addition to this, fault tolerance to single cell missing defect, single cell addition defect and single cell displacement defect of the proposed XOR gate has also been presented. Based on the performance evaluation, it is seen that the proposed XOR gate has least cell count, least area and least latency which in turn leads to least circuit cost. Also, the proposed design dissipates least energy. The applicability of proposed XOR gate has also been investigated by designing various cost efficient digital circuits such as full adder, parity checker, etc.

Efficient Nano-Scale Design of TIEO Based Reversible Logic Toffoli Gate Priority Encoder in Quantum-Dot Cellular Automata

The goal of this research is to create a QCA-based reversible priority encoder. It is one of the most crucial parts of the encoding and decoding process. This novel nanotechnology, known as quantum-dot cellular automata (QCA), shows promise as a foundation for the development of reversible circuits. This paper proposes a simple, reversible, 4-2 line priority encoder design for the QCA platform. Using the simple and cheap Toffoli gate architecture, a reversible encoder circuit may be built. To analyze the proposed designs’ structural soundness, the simulation program QCA Designer is used.

An efficient XOR design based on NNI and five-input majority voter in quantum-dot cellular automata

An efficient XOR design based on NNI and five-input majority voter in quantum-dot cellular automata

A new design of a digital filter for an efficient field programmable gate array using quantum dot technology

Digital filtering algorithms are most frequently used to implement generic-based Field-programmable gate arrays (FPGAs) chips, which are used for higher sampling rates. In the filtering structure, delay and occupied areas play a vital role. Since the existing structures suffered from shortcomings such as high delay and high occupied area, implementing a high-performance digital filter circuit with high speed and low occupied area based on unique technology can significantly improve the performance of whole FPGA structures. One of the best technologies to implement this vital structure to solve these shortcomings is quantum-dot cellular automata (QCA) technology. This paper presents several new efficient full adders for digital filter applications based on quantum technology, including a multiplier, AND gate, and accumulator. The QCADesigner 2.0.3 tool is used to create and validate the suggested designs. According to the results, all designed circuits have simple structures with few quantum cells, low area, and low latency.